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- Path: news.cis.nctu.edu.tw!usenet
- From: don_w1@verifone.com (Don Ward)
- Newsgroups: comp.sys.m68k
- Subject: Re: MC68LC302 -- PNDDR & PNDATA Addresses; Also RISC Microcode Question
- Date: Tue, 30 Jan 1996 16:00:20 GMT
- Organization: Dept. of Computer & Information Science, NCTU, Taiwan
- Message-ID: <4elfbu$huo@news.cis.nctu.edu.tw>
- References: <310AD218.691B@verifone.com>
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-
- Don Ward <don_w1@verifone.com> wrote:
-
- >I am writing device drivers for a board containing an MC68LC302 chip. This
- >involves "bit-banging" via some bits of the new (i.e. not present on the
- >regular MC68302 chip) I/O port controlled by PNDDR and PNDAT locations in the
- >dual-port RAM. The board is hooked up to a PC for cross-development using
- >Microtec tools including the Xray debugger and am puzzled by a couple of
- >things:
-
- >(1) I can not talk to the new I/O port using Motorola's published address
- >ofsets of PNDDR = $8DC and PNDAT = $8DE. My BAR is set to $FFF000 to allow
- >short negative addressing. I've tried setting PNDDR to all 1's, which should
- >allow me to write to PNDAT and then read back what I wrote but PNDDR and
- >PNDAT always read back both 0's no matter what I write to them. I'm also not
- >seing any level changes on the pins out from the MC68LC302 chip. Both byte
- >and word writes and reads have been tried on this port.
-
- >Ports A and B behave normally and predictably -- only port N is giving
- >trouble.
-
- >My suspicion is that either there is a secret (i.e. undocumented) bit
- >somewhere in another dual port RAM location to enable the PN port, OR the
- >published addresses for PNDDR and PNDAT are wrong. The supplementary
- >handbook says very little about this new port, other than it doesn't have a
- >control register (i.e. there is no PNCNT because the pins are ALWAYS meant to
- >be used for parallel I/O, never as "peripherals").
-
- >(2) The reason for the "bit banging" is that the 68302 definitley does NOT
- >support the protocol I'm using, which involves turning the line around in the
- >middle of the stop bit of an 8-bit+parity packet. The protocol requires the
- >RECEIVER to drive the line "low" for 1 bit time starting 1/2 bit time after
- >the end of parity bit if parity is incorrect. Rather weird but it's part of
- >an International standard (ISO 7816 part 3) and I have no choice but to
- >comply.
-
- >We would LIKE to microcode this protocol using the 68302's built in RISC
- >processor but Motorola are not very forthcoming with information on how to do
- >this. Microcoding would save a tremendous amount of processor load -- we
- >NEED to run at 9600 baud and would LIKE to run at 19200 and 38400.
-
- >So my question is -- have you or anyone you know ever successfully microcoded
- >a 68302. Please reply if you have so this can be taken further.
-
- >Thanks == Don Ward ==
-
- This is a followup to my own posting:
-
- On contacting Motorola we were told that the MC68CL302 chip we have is
- Rev. A and that certain functionality, including Port N, is missing
- fro this revision. They are FedExing us some Rev. B chips which
- apparently DO have Port N implemented.
-
- I wonder if this is common place in the chip industry? Nobody from
- Motorla bothered to inform us that we had a defective chip until I
- discovered the strange behavior and one of our hardware guys called
- Motorola. They were very helpful once contacted, but we feel they
- should have taken the initiative.
-
- Incidentally we just purchased a very expensive Orion I.C.E. and on
- checking found that it, too, contains the defective chip!
-
- == Don ==
-
-